1. Field of the Invention
The invention relates to a method of manufacturing a multi-chip stacking package, especially to a method of manufacturing multi-chip package using flip-chip bonding to complete the chip stacking.
2. Background of the Invention
Toward the increasing requirements for portability of electronic consumer products, undoubtedly the multi-chip module packaging technology is the best way to meet such requirements. However, the technologies for integrating the functions of many chips and reducing the area occupied by the package mostly need to stack the chips into a packaging device of 3-D structure.
FIG. 1 shows a cross-sectional schematic view of a conventional multi-chip stacking package 10, which is disclosed in the specification of Taiwan Patent Publication No. 444,364. The package 10 is characterized in that the active surface of the first chip 11 is welded to the upper surface of the substrate 15 with a plurality of bumps 13. Furthermore, the passive surface of a second chip 12 is attached to/onto the passive surface of the first chip 11. The upper surface of the active surface of the second chip 12 provides a plurality of wire bonding pads 17, which are connected to the wire bonding pads 17 and the bonding pads 18 of the substrate 15 through a plurality of metal bonding wires 14. The drawback of the package 10 in FIG. 1 is that the wire span of the metal bonding wire 14 is so long due to the connection from the wire bonding pad 17 of the second chip 12 to the bonding pad 18 of the substrate 15, such that a wire sway problem will rise easily and causes a short circuit during the process of encapsulation. Because the wire bonding process has a limitation for the height of wire arcs, it is necessary to keep a fixed space between the second chip 12 and the encapsulant 16, which results in a larger thickness of the package 10.
FIG. 2 shows another cross-sectional schematic view of the conventional multi-chip stacking package 20, which is disclosed in the specification of Taiwan Patent Publication No. 426,220. The package 20 attaches the passive surface of the first chip 11 onto the upper surface of the substrate 21 with the active surface of the first chip 11 facing upward. A second chip 12 is stacked and bonded with the first chip 11 by flip-chip bonding. The periphery of the active surface of the first chip 11 provides a plurality of wire bonding pads 25, which use a plurality of metal bonding wires 23 to connect with the bonding pads 18 on the substrate 21. The package 20 is superior to the package 10 in that the metal bonding wires 23 provide a shorter wire span and results in a higher yield. In addition, the structure of the package 20 is thinner and provides a better space applicability. However, in that prior patent specification, how to complete the flip-chip bonding for the two chips was not disclosed explicitly, and the structural characteristic of the combination part of the two chips was not presented in detail, either.
The first object of the invention is to provide a method for manufacturing a multi-chip stacking package so as to improve the production yield and production steps.
The second object of the invention is to provide a method of manufacturing a multi-chip stacking package with a low profile.
In order to achieve above-mentioned objects, the invention discloses a method of manufacturing multi-chip stacking package. The multi-chip stacking package uses at least two chips, which are bonded together and stacked by flip-chip technique, wherein the chip underneath is attached to/onto a substrate with glue. Each of the at least two chips has an active surface, and the active surface provides a plurality of bonding pads, in which the bonding pad is configured with Under Bump Metallurgy (UBM) and bumps based on the levels. The active surface of the chip underneath further provides a plurality of wire bonding pads on its periphery, and connects the wire bonding pads to the bonding pad of the substrate via the metal bonding wires. The whole package uses an encapsulant to protect the internal circuit and a plurality of solder balls are formed under the substrate so as to electrically connect to the circuit board. The characteristic of the invention is that after the alignment of the bumps of at least two chips, welded bumps will be generated in a high temperature welding to form a welded bump. Furthermore, one of the at least two chips may only provide a bonding pad similar to the Under Bump Metallurgy 43 and may not provide with bumps, and using the bonding pad to be welded with the bump on another chip.